1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, in particular, to the formation of an electric conductive region through the solid phase diffusion of impurities.
2. Description of the Related Art
As for the memory cell structure of DRAM which is constituted by one MOS transistor and one capacitor, there is known a trench type cell wherein a trench is formed in a semiconductor substrate and the inner wall portion of the trench is employed as a capacitor. In this trench type DRAM cell, the source/drain of MOS transistor is required to be electrically connected with one of the electrodes of the capacitor.
As for the technique for connecting the source/drain of MOS transistor to one of the electrodes of the capacitor, there is known a method wherein As(arsenic)-doped polycrystalline silicon is buried in a deep trench formed in a semiconductor substrate and As in the As-doped polycrystalline silicon is caused to diffuse through solid phase diffusion from the side-wall of upper portion of the trench, thereby forming an As diffusion region in the semiconductor substrate (see, for example, U.S. Pat. No. 5,360,758 and U.S. Pat. No. 6,110,792).
As for the method to minimize the junction leak current from a high-concentration As diffusion region which is formed by making use of the aforementioned method, it is conceivable to fabricate a structure where the high-concentration As diffusion region is enclosed by a low concentration P (phosphorus) diffusion region.
This structure can be fabricated by a method wherein P is introduced, through ion-implantation, into the As-doped polycrystalline silicon buried in the trench, thereby effecting the solid phase diffusion of As and P from the polycrystalline silicon. However, the doping of P by means of ion-plantation is accompanied with a problem that the introduction of P into a predetermined depth in the vertical direction is limited, thereby raising various problems. For example, when it is desired to introduce P into a deep region of the trench by means of ion-implantation using a high accelerating voltage of several tens KeV, a long period of heat treatment is required due to a long distance required for achieving the solid phase diffusion, thereby making it impossible to suitably control the diffusion region. As a result, the P thus diffused may badly affect the neighboring transistor which is spaced away by a distance of 500 angstroms from the edge of the trench, thereby raising problems such as the punch-through of transistor.
When P is introduced into a shallow region of the trench through ion-implantation using, for example, a low accelerating voltage of 5 KeV or less in order to inhibit the generation of the aforementioned phenomenon, it may be possible to form a diffusion region of P at a surface region of the As-doped polycrystalline silicon layer, thus making it possible to cover the top surface of As-doped polycrystalline silicon layer with a P diffusion region. However, it is difficult to cover the bottom of the As-doped polycrystalline silicon layer with a P diffusion region by diffusing P into a depth of 1000 angstroms or so. Therefore, it has been impossible to sufficiently enclose the As diffusion region with a low concentration P diffusion region, thus making it difficult to minimize the junction leak current at the As diffusion region.